1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, a semiconductor integrated circuit design method, and a semiconductor integrated circuit design apparatus and in particular to smaller area, speeding up, and lower power consumption to which a substrate control technology is applied in a semiconductor integrated circuit having MOS transistors.
2. Description of the Related Art
In a semiconductor integrated circuit, the substrate potential of a MOS transistor (MOS element) may be controlled for use, because there is a feature that the threshold value and the saturation current characteristic of the MOS transistor can be made variable by changing the substrate potential of the MOS transistor. As an example of making the most of the feature, a method of making the substrate potential of the MOS transistor variable between the operation time and the stop time of the semiconductor integrated circuit is available. Specifically, the following method is available: When the semiconductor integrated circuit operates, the potential difference between the substrate potential and the source potential of the MOS transistor is set to zero and when the semiconductor integrated circuit stops, the potential difference between the substrate potential and the source potential is taken large, whereby the threshold value of the MOS transistor at the stop time is made larger than that at the operation time and the subthreshold leak current of the MOS transistor is reduced, whereby lower power consumption is accomplished. (Refer to non-patent document 1.)
To implement the substrate control of the MOS transistor described above, a layout technique to provide good area efficiency of a semiconductor integrated circuit is proposed. (Refer to patent document 1.)
Further, a method of implementing a layout while maintaining high speed and lower power consumption by supplying separate substrate potentials to different substrates at the operation time is proposed. (Refer to patent document 2.)
On the other hand, the following method is also proposed: According to a forward substrate voltage application control technology (FBB substrate control technology) for applying a higher voltage than that of the source of a MOS transistor to the substrate of the MOS transistor, the threshold value of the MOS transistor is decreased, characteristic variations in the MOS transistor are suppressed, and operation at the usual power supply voltage or less is made possible, whereby further lower power consumption can be accomplished. (Refer to non-patent document 1.)
Non-patent document 1: T. Kuroda et al., “A High-Speed Low-Power 0.3 urn CMOS Gate Array with Variable Threshold Voltage Scheme,” IEEE Custom Integrated Circuit Conference 1996 PP. 53-56
Non-patent document 2: M. Miyazaki et al., “A 175 mA Multiply-Accumulate Unit Using an Adaptive Supply Voltage and Body Bias (ASB) Architecture,” IEEE ISSCC 2002 3.4
Patent document 1: Japanese Patent No. 3212915
Patent document 2: Japanese Patent No. 3777768
Hitherto, various technologies have been proposed as described above; a unique substrate potential had been supplied to one substrate forming a MOS transistor (for NMOS, the substrate is PWELL and for PMOS, the substrate is NWELL). Therefore, to supply a different substrate potential to each MOS transistor, separate PWELL and NWELL are formed, WELLs of the same polarity must be physically isolated, and there is a problem of a disadvantage with respect to the area as compared with the case where the substrates of all MOS transistors are set to the same potential. Further, as for placement of substrate contacts, hitherto, the distance between the substrate contacts has not been defined and the number of substrate contacts may become more than the necessary number for implementing the essential characteristics of a semiconductor integrated circuit; there is also a problem of furthermore increasing the area of the semiconductor integrated circuit.
To give a different substrate potential to each WELL, although the speed at the operation time can be improved, a passage which need not be speeded up in each MOS transistor on one WELL also becomes high speed and there is a problem of an increase in leak current, etc. Particularly, as described above, in the forward substrate voltage application control technology for applying a higher voltage than that of the source of a MOS transistor, if the source-substrate voltage of the MOS transistor is set to one voltage value or more, the leak current increases because of the effects of a forward diode and a parasitic bipolar. Therefore, the forward substrate voltage application control technology cannot apply a so large substrate voltage and cannot much contribute to performance improvement of MOS; this is a problem of the technology.
That is, a method of implementing a layout for making it possible to accomplish speeding up and lower power consumption more finely while maintaining a smaller area in a semiconductor integrated circuit requiring different substrate potentials does not exist.